1. Field of the Invention
The disclosed technology is relates generally to a semiconductor device including a diode, which can be integrated in integrated circuit packages provided with Electrostatic Discharge (ESD) protection on an interposer chip.
2. Description of the Related Technology
As a cost-reducing measure in IC-packaging, it is known to produce electrostatic discharge protection circuitry on the interposer chip instead of on the IC's themselves. This is described for example in document U.S. Pat. No. 5,644,167 and may be referred to as the introduction of an ‘active interposer’. An advantage of this approach is that the processing cost of the IC package is reduced. As a larger area is available on the interposer, older CMOS technology manufacturing nodes can be applied on the interposer, leading to a further cost reduction, e.g. 65 nm node technology is used on the interposer compared to 32 nm node or less on the IC's.
However, the IC-packaging industry continues to look for improvements in terms of cost-effectiveness of the applied processes. ESD protection devices are major examples of semiconductor devices comprising a diode junction. For this type of device, as for others comprising a diode junction, an optimization is needed in terms of the process technology itself, such as the number of process steps and the number of lithography masks applied in the process, in order to further obtain a cost reduction in the production of such devices, for example on an interposer chip.